Get your dream job within 2 days (HURRY UP)ENROLL NOW
+

ASIC Design Engineer

Synaptics Incorporated – San Jose , CA



Digital Logic design fundamentals, SoC design and integration



Salary : $50000 - $70000  / YEAR

Requirements BSEE/MSEE with 2+ years of experience Good experience with Digital Logic design fundamentals, SoC design and integration Hands on experience with Verilog Coding Hands on experience with Logic Synthesis using Design Compiler and Static Timing Analysis with Prime Time Working knowledge of integrating IP blocks with AMBA AXI/AHB interfaces to SoC Fabric and performance analysis is a strong plus Strong knowledge of PERL, Shell scripting The candidate will be responsible for SoC Design/Integration, Synthesis, Equivalence Check, linting/CDC Analysis, and Static Timing Analysis for multi-million gate SoCs targeted for Voice Assistant & Multimedia applications. The candidate will also be responsible for RTL/gate level Power Analysis and Optimization. Would work with other members of the team to optimize the PPA in creating the most cost effective SoCs.

Recommended jobs for you

  • Chip and Package Signal/Power Integrity Technologist

    Google Sunnyvale, CA

    View Job
  • DDR PHY Design Engineer

    Intel San Jose, CA

    View Job
  • IC Design Engineer

    Broadcom San Jose, CA

    View Job
  • IC Design Engineer

    Broadcom San Jose, CA

    View Job
  • IC Design Engineer

    Broadcom San Jose, CA

    View Job

Thanks For Your Feedback

Attach A Resume First