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Hardware chip logic design engineer


Job Id : 7037

Jobtitle : Hardware Chip Logic Design Engineer

Location : San Jose, CA

Company Name : Artech Information Systems LLC

Industry : Information Technology

Salary : $50,000 - $93,000  YEAR

Job type : Contractor

Posted on: 2019-11-12


Required Skills : SystemVerilog, Verilog, VHDL, ASIC EDA Tools, Chip Design,

Benefits : No benefits are available


Job Description:  

  • Read and comprehend a high-level, functional specification of a processing unit
  • Clearly and concisely code the intended function of the processing unit in SystemVerilog (starting from an empty file)
  • Structure the code to be both modular and parameterized
  • Follow the project's SystemVerilog coding guidelines/style guide
  • Correct all LINT errors
  • Implement a self-checking testbench (such as UVM) to test functional correctness of the unit
  • Add assertions for checking design correctness
  • Follow pipeline timing for unit as specified by the architectural specification
  • Use best practices for inserting register stages
  • Run synthesis tools and update design to achieve timing closure
  • Implement/code for clock gating and data gating to achieve power reduction
  • Run synthesis tools to estimate area and power
  • Create simulation stimuli at realistic activity factors
  • Run gate-level simulations and measure power using realistic activity factors
  • Participate in design and code reviews, addressing and implementing all feedback

 

Required skills/Level of Experience :

  • Chip design experience with functional and structural SystemVerilog
  • Familiarity with industry standard ASIC EDA tools, including logic simulators, synthesis, timing closure, and power optimization

 

Desired skills:

  • At least 3 year experience in any of the following: SystemVerilog, Verilog, or VHDL--including simulation and timing closure
  • At least 1 year in Scripting, Tcl and Python preferred
  • Experience with DFT insertion (scan-chains, LBIST, MBIST)
  • Experience with 3rd party IP integration

   

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