Design Verification Engineer
Job ID : 27767
Job Title : Design Verification Engineer
Location : San Francisco, CA
Comapny Name : OPTnation
Job Type : Full-Time
Industry : Engineering
Salary : $100000 - $130000 per year
Work Authorization : ["OPT","Have H1 Visa","US Citizen"]
No. of Positions : 2-4
Posted on : 08-31-2021
Required Skills : UVM , Python3/Bash/Tcl , Verdi/VCS , ASIC/SOC
Benefits : Medical Insurance, Life Insurance
Job Description :
Skills and Qualification Required:-
Minimum Qualification :-
o BSEE/MSEE/BSCompE/MSCompE with 5 years of industry experience .
o 3+ years of UVM experience (so this implies 3+ years of SystemVerilog as well).
o Deep understanding of coverage, constrained-random, transaction level .
o Experience with Verdi/VCS is a must
o Experience with test plan documentation
o Familiarity with Python3/Bash/Tcl scripting is a must
o Experience with debugging simulation failures to guide digital design. Experience with fixed point arithmetic
Preferred Qualifications :-
o BSEE/MSEE/BSCompE/MSCompE with 10 years of industry experience .
o Experience with performance analysis and performance characterization a plus.
o Experience with using Hierarchical Verification Plan is a plus.
o Experienced with a full ASIC/SOC tapeout from beginning to end.
o Experience with video processing or graphics pipelines is a plus.
o Experience with floating point arithmetic in addition to fixed point arithmetic.
o Mininum 5-20 yrs.
Company Details :
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